CPU targets
pxx emits native and cross-target code from a single compiler invocation
(--target=ARCH), all lowering from the shared IR — no vendor toolchain in the
loop. Cross-target Linux binaries run under QEMU user-mode via
tools/run_target.sh.
| Target | Status | Notes |
|---|---|---|
x86_64 |
Full | Native Linux ELF — the default backend and the self-host host. |
i386 |
Full | 32-bit Linux ELF. |
aarch64 |
Full | 64-bit ARM Linux ELF. |
arm32 |
Full | 32-bit ARM Linux ELF. |
riscv32 |
Full | 32-bit RISC-V — Linux ELF and ESP32-C3 (RV32IMC), bare metal or ESP-IDF. Linux riscv32 has no threads and no Nil Python; both are refused with a message. |
xtensa |
Partial | ESP32-S3 (LX7) and classic ESP32 (LX6) run on boards through ESP-IDF; ESP32-S2 compiles only; bare metal under QEMU. Some ABI corners (e.g. windowed-ABI interrupt vectors) are still limited. |
wasm32 |
Partial | Runs under wasmtime. The least tested target: its suites are run by hand. No threads. |
Threads (TThread, C pthread_create, parallel for) work on x86-64, i386,
aarch64 and arm32, and each thread has its own threadvar and C __thread
copy there (measured with pin v446 under QEMU).
64-bit integer arithmetic is available and oracle-validated on every target.
Floating point on the ESP cores is soft-float, linked in automatically when a
program uses a float (no uses needed) — there is no FPU codegen path. Real is
Single there.
See the documentation: Targets · Cross-compilation · ESP32 / microcontrollers.