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ESP32 managed-feature port (xtensa + riscv32, qemu-validated)

Motivation

Stage-1 ESP codegen (done/feature-target-esp32) only ran procs/params/calls/ loops/ifs/globals/int arith. This arc brings the managed-runtime spine to both ESP ISAs and, critically, establishes a runnable output-equality harness so ESP features are validated against the x86-64 oracle on real Espressif QEMU, not just llvm-mc encodings.

What landed

Harness. tools/esp_run.sh [--chip esp32s3|esp32c3] <prog.pas> compiles for the chip's ISA, links it as app_main via examples/esp32/hello-{s3,c3}, merges a flash image, boots it under the Espressif qemu-system-{xtensa,riscv32} fork, and prints exactly what app_main wrote (IDF banner + trailing qemu signal stripped, serial CRLF→LF). Output is diffed against the program's x86-64 run. Heavy / env-dependent (needs . ~/esp/esp-idf/export.sh), so NOT in make test.

Codegen / runtime, both ESP backends (unless noted):

Validated (qemu, both esp32s3 + esp32c3, == x86-64 oracle)

test_esp_{print,hello,heap,dynarray,aoc,cast}.pas — ints/recursion (1..5/15), fixed bytes (PXX/OK), heap (100/20/3/123), dynarrays (5/150/2/30), array-of-const writeln (1 2 3 / 42 -7 100 999), casts (ABZ!). make test + self-host byte-identical after every step.

Acceptance

Notes / follow-ups