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Complex as a packed-double XMM value (SSE2/SSE3)

Idea

A complex double is (re, im) = 2×f64 = exactly one XMM register (re in lane 0, im in lane 1). Lower complex arithmetic to packed-double SIMD instead of two scalar doubles + shuffling:

Baseline caveat (ties to the CPU-feature-level question)

addsubpd/movddup are SSE3 = x86-64-v2, NOT the guaranteed v1 baseline (SSE2). v2 is ~universal (every x86-64 CPU since ~2005), so requiring it is usually fine — but for strict-v1 portability, emulate the sign flip on SSE2: mulpd the cross terms, xorpd a {0.0, -0.0} mask onto one lane, addpd (one extra op vs addsubpd). Decide per the arch policy ([[feature-opt-arch-level-and-dispatch]] if raised): plain packed add/sub is v1; complex-mul is v1-with-emulation or v2-native.

Storage / residency note

A complex resident is the ONE case that needs the full 16-byte save (movaps/movups), not the 8-byte scalar movsd — both lanes are live. Feeds into [[feature-opt-pxx-internal-abi-unified-residency]] (a complex value = one 16-byte xmm resident; align its frame slot to 16 for movaps).

Scope

Acceptance